All a-board!

All a-board!

Saturday 21 April

So the boards came back from Seeed icon_smile I took a moment to make sure I was static-neutral w.r.t them, and then opened up the first board. The boards looked really good with all the chips in the right place and orientation, but then my eye caught the area around the XMOS chip and my heart skipped a beat... There were several solder-bridges on the 0.4mm pins...

Stacks Image 1401

The whole point of sending them off for assembly was to get a clean well-soldered placement of this chip in particular. The other ones are much easier because they have larger separation between the pins. A moment later I realized these bridges were probably by intent - it's been so long since I designed the circuit that I'd forgotten the details. Looking at the CAD design...

Stacks Image 1410

there is a 1:1 correlation between the "solder bridge" and the points where the pins are joined together. Typically it's VCCINT or VCCIO, but RST_N and TRST_N are also tied together on the XTAG interface.
So I haven't had time to solder up a board to start the bring-up, but here's what one looks like before I start attacking it with a hot air gun..

Stacks Image 1419

... which looks pretty good to me. Notably absent is U$9 (I guess they didn't have any in-stock, which isn't much of a surprise), so I'll have to order some of the larger form-factor size chips. I'm pretty busy in work for the next two weeks (got a demo to give at the end of next week) so I'm not sure how quickly I'll get to starting bring-up, but I'm pretty pleased with the end-results so far...

Now let's just hope the design was correct icon_smile